The threshold voltage of the PMOS Transistor is normally the ‘Vgs’ which is necessary to create the channel known as channel inversion. The truth table of the above logic circuit is given below. So, this logic gate will generate a logical ‘0’ because it is detached from the source by an open circuit & is connected to the GND through a closed circuit.

The B input of pMOS will generate a ‘0’ & B input of nMOS will generate a ‘1’. Consequently, we should verify the B input of pMOS & nMOS also. When A is ‘1’ & B is ‘1’, then A input of” pMOS will produce a zero, and A input of nMOS will generate ‘1’. So, this logic gate will generate a logical 1 because it is connected to the source through a closed circuit & detached from the GND by an open circuit. When A is ‘1’ & B is ‘0’, then the ‘B’ input of pMOS will generate high output (1) & ‘B’ input of NMOS will generate an output as low (0). Thus, this gate will produce a logical one because it is connected to the source through a closed circuit and detached from the GND by an open circuit. When A is ‘0’ & B” is ‘1’, then A input of pMOS will generate a ‘1’ & A input of NMOS will generate a ‘0’. NAND Gate Design with PMPS & NMOS Transistors So, this logic gate generates a logical ‘1’ because it is connected to the source by a closed circuit & detached from the GND through an open circuit. In the below logic circuit, if the input A is 0 and B is 0, then A input of pMOS will produce ‘1’ and A input of nMOS will produce ‘0’. If any of the two inputs are LOW (0), then it gives high output results. The output of this gate is low (0) only if the two inputs are high (1) and its output is a complement to an AND gate. Generally, a NAND gate in digital electronics is a logic gate which is also called a NOT-AND gate. The NAND gate design using the PMOS transistor and NMOS transistor is shown below. So, VSS signifies the logic ‘0’ and it is also set normally to 0V. The low voltage is frequently known as GND or VSS. At present transistors cannot actually withstand such high voltages because they typically range from 1.5V – 3.3V. The VDD voltage levels in TTL logic were generally around 5V. The transistor’s positive voltage is known as VDD which represents the logic high (1) value within digital circuits. Whenever these transistors deal with digital logic there are usually have two different values only like 1 & 0 (ON and OFF). Whenever the voltage gets low sufficiently then the channel will be inverted and creates a conducting pathway from the source terminal to the drain by allowing the flow of current. Once the voltage supply at the gate terminal is lowered, then positive charge carriers will be attracted to the bottom of the Si-SiO2 interface. Once this happens, there is no flow of current, so the transistor will be turned OFF. Once the gate terminal is positive, then the source & drain terminals are reverse-biased. In the pMOS transistor, the body is held at +ve voltage. This transistor has a controlling gate as shown in the diagram which controls the electrons flow between the two terminals like source & drain. A pMOS transistor is built with an n-type body including two p-type semiconductor regions which are adjacent to the gate. The cross-section of the PMOS transistor is shown below. Once we merge them into a single MOS circuit, then it will become a CMOS (complementary metal-oxide semiconductor) circuit. So the function of the PMOS transistor and NMOS transistor is quite opposite. If the gate terminal provides a 1 voltage, then this inverter will change it into zero and functions the circuit accordingly. So the main function of this circle is to invert the input voltage value. This bubble is also known as an inversion bubble. Similarly, this transistor forms a closed circuit when it gets a voltage at around 0 volts which means the current flows from the gate (G) terminal to the drain (D).

This transistor will form an open circuit whenever it gets non-negligible voltage which means, there is no flow of electricity from the gate (G) terminal to the source (S). The p-type transistor working is quite opposite to the n-type transistor. PMOS Transistor Symbol How Does PMOS Transistor Work? The PMOS transistor symbols are shown below. In this transistor, the charge carriers like holes are responsible for the conduction of current. These transistors have three main terminals the source, the gate & the drain where the transistor’s source is designed with a p-type substrate, and the drain terminal is designed with an n-type substrate. This transistor is exactly the reverse of the NMOS Transistor. The PMOS transistor or P-channel metal oxide semiconductor is a kind of transistor where the p-type dopants are utilised in the channel or gate region.

Cmos transistor diagram